Standard and Programmable IPs
With a team of first class design engineers with 108 Malaysia, USA & China patents filed, SkyeChip offers high-performance standard and programmable IPs on advance process nodes.
Programmable IPs for FPGA
With our team’s in-depth experience in FPGAs, we also specialize in developing customized programmable IPs to meet any unique requirements.
Memory Interface IPs
HBM3/3E PHY & Controller
Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 (JESD238A) JEDEC standards
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 6400 MT/s for HBM3 and up to 9600 MT/s for HBM3E
- DFI 5.1 compatible interface to the memory controller
- Flexible PHY with programmable intelligent interface training sequences
- Flexible IEEE1500 interface to support memory vendor customizations
- Supports up to 32Gb density per die
- Supports up to 16H HBM3 DRAM stacks
- Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs
- Add-on features/engines for MPFE, RAS and Debug available upon request
- Add-on feature for generic 2.5D die-to-die data transport interconnect
DDR5/4 PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC standards
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 4800 MT/s rates with upgradable option to 6400 MT/s
- DFI 5.0 compliant interface to the memory controller
- I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)
- Flexible PHY with programmable intelligent interface training sequences
- Supports x4, x8 and x16 SDRAMs
- Supports up to 64Gb addressing for DDR5 and up to 32Gb addressing for DDR4
- Supports 3DS extensions up to 16H for DDR5 and up to 8H for DDR4
- Supports up to 4 ranks for components, UDIMM, RDIMM and LRDIMM
- Add-on features/engines for MPFE, RAS, Ping-Pong and Debug available upon request
LPDDR5/5X PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to LPDDR5/5X (JESD209-5C) JEDEC standard
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 6400 MT/s rates with upgradable option to 10667 MT/s
- DFI 5.1 compliant interface to the memory controller
- I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)
- Flexible PHY with programmable intelligent interface training sequences
- Supports x8, x16 and x32 SDRAMs
- Supports up to 32Gb addressing
- Supports up to BG, 8B and 16B bank modes
- Add-on features/engines for MPFE, RAS and Debug available upon request
Interconnect IPs
Non-Coherent Network-on-Chip (NOC)
Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resulting in power and area efficient ICs
- Node Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
- Architected to reduce routing congestion and to ease high frequency timing closure
- Supports operating frequencies up to 2GHz
- Supports source synchronous and synchronous clocking topologies
- Supports 2.5D and 3D die-to-die NOC bridging
- Integrates seamlessly with SkyeChip’s Coherent NOC for partitioned interconnect systems
Coherent Network-on-Chip (NOC)
Scalable and area efficient interconnect solution optimized for memory coherent systems
- Node Protocols: ACE4, ACE5 and CHI
- Architected to significantly reduce routing congestion for many-core systems
- Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
- Supports operating frequencies up to 2GHz with assists in high frequency timing closures
- Supports source synchronous and synchronous clocking topologies
- Integrates seamlessly with SkyeChip’s Non-Coherent NOC for partitioned interconnect systems
UCIe PHY & Controller
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.
- Supports transfer rates of up to 32 Gbps/pin for up to 8Tbps with 10.5Tbps/mm of die edge bandwidth
- Supports PCIe, CXL and streaming protocols adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies
- Built-in link initialization
- Supports major 2.5D inter-die packaging technologies and standard packaging technologies
- Supports internal and external (PHY-to-PHY) loopback test
- Supports built-in self-test and repair functionality to maximize post-package yield