Join Us Where You Are Valued,
SkyeChip takes pride in competing at the global level with our IPs and IC products. There are endless opportunities at SkyeChip for our employees to explore, grow and excel. It is about working for a company where you are most valued, challenged and inspired in your job.
Every Experience Level is Welcome!
We provide growth opportunity for all
No matter what your starting positions, we are committed to help you to reach your full potential and beyond.
New college graduates are encouraged to apply. SkyeChip is the perfect place to launch your career.
Positions Available
Logic Design Engineers (Senior/Intermediate/Junior)
- As a member of our Digital Design team, you will collaborate with architects, design verification engineers, software engineers, and circuit designers to and deliver world-class solutions
- Responsible for the logic and/or verification of the design including RTL design, synthesis, verification plan reviews and timing analysis using leading edge CAD tools on the latest process technologies
- Day to day tasks include: writing readable high performance and low power RTL, synthesis and timing closure, execute test/coverage plans, design verification and debug, and work with physical design engineers to achieve best timing, area, performance and power goals
Design Verification Engineers (Senior/Intermediate/Junior)
- As a member of our Digital Design team, you will collaborate with architects, logic design engineers, software engineers, and circuit designers to and deliver world-class solutions.
- Responsible for the verification of the design and executing functional verification using leading edge CAD tools on the latest process technologies
- Define and create test plans for RTL validation, develop coverage-driven system verilog/UVM test benches
- Run both RTL and gate-level simulations and regressions, debug and implement corrective measures for failing tests
- Capacity could include full chip/system functional verification (defining verification strategies, methodologies and test plan to enable effective verification)
- Work with design engineers to perform logic synthesis and equivalence check
- Collaborate with design engineers of other discipline on the overall IP implementation
Circuit Design Engineers (Senior/Intermediate/Junior)
- Work as part of a team to design and implement high speed interfaces and complex mixed-signal circuits using state-of-the-art sub-micron CMOS technologies and various EDA tools.
- High speed analog and hybrid Phase Locked loops and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, interpolator circuits, high speed buffers etc.
- Contribute to architecture development and transistor level circuit design of high performance RX/TX and associated blocks like VREG, comparators, digital state machines for DDR/HBM memory interfaces
- Work closely with mask design engineers to deliver the physical design as well as work with characterization groups for silicon evaluation.
- Perform architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
Physical Design Engineers (Senior/Intermediate/Junior)
- Responsible for unit/block/chip level RTL to GDSII Physical design activities at block and/or CPU level.
- Collaborate with the microarchitecture and RTL teams to achieve aggressive performance, power, and area (PPA) goals.
- PD activities includes floor plans, global signal planning, Synthesis, Place and Route, Static Timing Analysis, block/chip level integrations.
Custom Layout Engineers (Senior/Intermediate/Junior)
- Perform physical layout for mixed-signal functions like PLL’s, high speed I/O circuits, general I/O’s, ESD structure designs in state-of-the-art sub-micron CMOS technologies using EDA tools.
- You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
- Job duties will include floor planning, custom layout, RC extraction, EM & IR drop, DRC’s & schematic to layout verification.
Software Engineers (Senior/Intermediate/Junior)
- Define and develop software architecture to optimize system performance for ASICs, SoCs and FPGAs
- Define and develop system modeling architecture for state-of-the-art memory and interconnect IP architectures
- Define and develop graphical user interface for system level optimizations
- Document and demonstrate solutions by developing documentation, flowcharts, layouts, diagrams, charts, code comments and clear code.
- Determine operational feasibility by evaluating analysis, problem definition, requirements, solution development, and proposed solutions.
Design Automation Engineers (Senior/Intermediate)
- Develop and test design engineering automation tools, create flows/scripts to automate design methodologies for digital, circuit, physical design and layout
- Evaluate EDA vendor capabilities to provide the required products or services
- Collaborate with design teams on methodology development to improve design and development efficiency
- Create custom tool flow and regression automation
- Understanding of layout design rules for advanced process nodes, circuits and Verilog preferred
- Good understanding in scripting/programming languages such as Python, TCL, Perl and C++ preferred
Silicon Package Design Engineers (Senior/Intermediate/Junior)
- Develop package and platform routing guidelines, with opportunity to work on advance 2.5D CoWoS packaging technology
- Definition and evaluation of circuit design features required to support interconnect performance requirements
- Drive and define the key enablers to deliver product landing zone for SIPI performance
- Perform signal and power routing on package substrate, component or die placement on the package substrate inclusive of extraction, simulation, analysis and validation of package signal and power integrity
- Perform time/frequency domain power integrity simulations and validate the simulation results.
- Interface with operation team and OSAT to engage with substrate design rules review and package assembly schedule
- Collaborate with silicon design team to review die bump floorplan and interface with customer engineering to understand the design requirements
- Perform RLCD and S-parameter extraction, simulations and analysis.
- Creation of signal measurement test plans and review of measurement results
- Characterization data validated against spec and collaborate fixes if needed to feedback on the next derivation silicon
DFT/DFD/DFM Engineers (Senior/Intermediate/Junior)
- Define and execute DFT strategy and methodologies
- Define test structures, debug structures, test plans for complex IP blocks and products
- Create test vectors or oversee their creation
- Collaborate with architecture, design, circuits and physical design team to close DFT/DFD/DFM requirements for IPs and products
- Validate DFT requirements are being met
- Work with designers to increase test coverage, debug observability and flexibility
- Verify post-PD designs meet DFT requirements
- Work with test personnel, stepping in to do run tests when needed
- Hands-on experience with commercial test generation tools and strong fundamental knowledge DFT techniques preferred
Internship Program
