IP Solutions

Standard and Programmable IPs

With a team of first class design engineers with more than 80+ US patents, SkyeChip offers high-performance standard and programmable IPs on advance process nodes.

Programmable IPs for FPGA

With our team’s in-depth experience in FPGAs, we also specialize in developing customized programmable IPs to meet any unique requirements.

Memory Interface IPs

HBM3 PHY & Controller

Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards

  • One stop PHY & Controller solution with an average random efficiency of more than 85%
  • Supports up to 6400 MT/s
  • DFI 5.0 compatible interface to the memory controller
  • Flexible PHY with programmable intelligent interface training sequences
  • Flexible IEEE1500 interface to support memory vendor customizations
  • Supports up to 32Gb density per die
  • Supports up to 16H HBM3 DRAM stacks
  • Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs
  • Add-on features/engines for MPFE, RAS and Debug available upon request
  • Add-on feature for generic 2.5D die-to-die data transport interconnect

DDR5/4 PHY & Controller

High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC standards

  • One stop PHY & Controller solution with an average random efficiency of more than 85%
  • Supports up to 4800 MT/s rates with upgradable option to 6400 MT/s
  • DFI 5.0 compliant interface to the memory controller
  • I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)
  • Flexible PHY with programmable intelligent interface training sequences
  • Supports x4, x8 and x16 SDRAMs
  • Supports up to 64Gb addressing for DDR5 and up to 32Gb addressing for DDR4
  • Supports 3DS extensions up to 16H for DDR5 and up to 8H for DDR4
  • Supports up to 4 ranks for components, UDIMM, RDIMM and LRDIMM
  • Add-on features/engines for MPFE, RAS, Ping-Pong and Debug available upon request

Interconnect IPs

Non-Coherent Network-on-Chip (NOC)

Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resulting in power and area efficient ICs

  • Node Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
  • Architected to reduce routing congestion and to ease high frequency timing closure
  • Supports operating frequencies up to 2GHz
  • Supports source synchronous and synchronous clocking topologies
  • Supports 2.5D and 3D die-to-die NOC bridging
  • Integrates seamlessly with SkyeChip’s Coherent NOC for partitioned interconnect systems

Coherent Network-on-Chip (NOC)

Scalable and area efficient interconnect solution optimized for memory coherent systems

  • Node Protocols: ACE4, ACE5 and CHI
  • Architected to significantly reduce routing congestion for many-core systems
  • Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
  • Supports operating frequencies up to 2GHz with assists in high frequency timing closures
  • Supports source synchronous and synchronous clocking topologies
  • Integrates seamlessly with SkyeChip’s Non-Coherent NOC for partitioned interconnect systems

Die-to-Die (D2D) Interconnect

Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead

  • Adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies
  • Architected to significantly reduce wiring overhead across multiple dies
  • Supports transfer rates of up to 6.4GT/s
  • Supports major 2.5D and 3D inter-die packaging technologies

Analog IPs

High-Speed PLL

  • Reference clock frequency range from 100Mhz to 350Mhz
  • FBDIV range: 2-32 (0.5 division)
  • POSTDIV range: 1, 2, 4, 8
  • VCO frequency can support range from 1.5GHz to 3.2Ghz
  • Output frequency range: 300MHz – 3.2GHz

Bandgap

  • Output Voltage: 0.9V +/- 1%
  • Output Current: 50uA +/- 10%
  • Buffer Strength: Up to 100uA sink load
  • Operating Temperature: -40C to 125C
  • Power Consumption: Less than 500uW

I/O IPs

MIPI D-PHY

  • Compliant with the MIPI D-PHY spec v2.5
  • Fully integrated hard macro with lane control and interface logic
  • Up to 1.5 Gbps per lane with upgradable option to 2.5 Gbps per lane
  • Supports PHY Protocol Interface (PPI)
  • Low-power escape modes and ultra low-power state modes

Configurable I/O

High-speed configurable I/O capable of signaling speeds of up to 3.2 GT/s supporting the following I/O standards

  • LVDS 1.5V
  • HCSL 1.2V
  • POD 1.1V & 1.2V
  • SSTL/HSTL/HSUL 1.2V
  • LVSTL 1.1V
  • LVCMOS 1.2V/1.5V

Processor IPs

Low Power RISCV CPU IP

  • RISC-V RV32 instruction set:
    • I > full support
    • M > partial support
    • C > full support
  • Machine mode only
  • 32 vectorized interrupts
  • Standard debug as defined per RISC-V

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