Job Posting

We are hiring

Please kindly send us your resume to hr@skyechip.com

Circuit Design Architect/Micro Architect

Responsibilities:
Mixed-signal architect/micro architect to help path finding, develop novel circuit architectures, resolve timing budgets, drive design development and work with customers to understand the marketing requirements and provide optimal engineering solutions . Communicate and drive the architectural specs to internal design teams in RTL, circuits, verification, physical implementation and layout teams.   As a start up, candidates has a lot of  opportunities to involve from architectural discussion, down until debug activities, both internally and externally. 

Logic Design Architect/Micro Architect

Responsibilities:

In charge of path finding, defining architectural/micro architecture specifications for various blocks, design & develop the RTL and work with stakeholders to ensure a robust IP design. The candidate will be involved in technical discussions with key design members in coming up with design high level specification and implementation details. As a start up, the candidates will have the opportunity to work directly with customers, understand customer use cases and integrate customer requirements in the IP solutions. Besides, he/she will be engaged with other architects in ensuring quality feature definition, logic development, timing closure and delivering optimal solution for our memory IP portfolio. 


Circuit Design Engineer

Responsibilities: 

In charge developing state-of-art high end analog IP using advanced deep-micron processes.  Job scope includes performing circuit design and simulations to check circuit quality, functionality, performance and reliability of analog circuitry.  As a start up, candidates has a lot of opportunities to work with designers/architects and other cross functional team to optimize the circuit design using advanced circuit design techniques.  Besides, candidates are having great opportunities to work with a cross site global team setup for the design closure. 

Logic Design Engineer

Responsibilities:

In charge developing state-of-art high end memory IP based on the JEDEC spec.  Job scope includes participating in the development of the memory IP, coming up with new memory design which can achieve better performance and power envelope.  As a start up, candidates has a lot of opportunities to work with designers/architects and other cross functional team to learn the best in class design techniques.  Besides, candidates are having great opportunities to work with a cross site global team to create world class optimum memory IP design. 

Design Verification Engineer

Responsibilities:

In charge of verifying various IP blocks in IP/sub system/full chip.  The job scope includes defining test plans, develop system verilog/UVM test benches, debugging and running regression to deliver a well coverage design.  Besides, the candidate may also get involved in Gate Level Simulation and emulation.  As a startup, candidates has a lot of opportunity to work with designers/architects and other cross functional team to validate the design.  Besides, candidates are having great opportunities to work with a cross site global team setup for the design verification and closure    

Physical Design Engineer

Responsibilities: 

In charge of IP/ASIC/SoC physical implementation and design closure, using state-of-art deep sub-micron process nodes in 16nm from RTL to GDS.  The job scope includes floor planning, synthesis, auto-place and route, clock tree planning & synthesis, static timing analysis, design closure and physical verification.   As a startup, candidates has a lot of opportunity to work with designers/architects and other cross functional team to optimize the design.  Besides, candidates are having great opportunities to work with a cross site global team setup for the design closure. 

Custom Layout/Mask Design Engineer

Responsibility:

Translating design schematic circuitry to physical layout artwork, using state-of-art process technology nodes in 16nm.  The job scope includes floorplanning, device placement, matching and routing, performing LVS, DRC, DFM & reliability verification.

As a startup, candidates has the opportunity to work with designers/architects to optimize the design.  Candidates are having great opportunities to work with a cross site global team setup for the design closure.

Interested to join us?

Drop us a line!

We would love to meet up with you for further discussions

We are continuously looking for talents, so feel free to drop by our office

SkyeChip Sdn Bhd

CREST Place, Block A, Sains@USM, 10 Persiaran Bukit Jambul, 11900 Bayan Lepas. Penang, Malaysia.

hr@skyechip.com